The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, more specifically to a semiconductor device including gate electrodes of a polymetal structure having laid polycrystalline silicon films and metal films, and a method for fabricating the same.
Conventionally, the gate electrodes of MOSFETs have been formed of single polycrystalline silicon layered structures owing to the thermal stability, the compatibility of polycrystalline silicon with silicon of the substrates in its MOS characteristics, etc. Presently, the so-called polycide structure, which is formed of a silicide film deposited on a polycrystalline silicon film, is dominantly used for the end of decreasing sheet resistance of the gate electrodes while utilizing the above-described advantages of polycrystalline silicon. Logic devices and memory devices now on market have gate electrode structures of the polycide structure.
The gate electrodes of the MOSFETs of the current logic devices generally have layered structures of titanium silicide or cobalt silicide, and polycrystalline silicon. On the other hand, the gate electrodes of the MOSFETs of memory devices are formed of layered structures of tungsten silicide and polycrystalline silicon. This is because the logic device require no high-temperature and long-time heat processing after the gate electrodes have been formed, so that titanium silicide and cobalt silicide, which have low heat resistance but can sufficiently lower sheet resistance, are applicable to the gate electrode of the logic device for high-speed operation. On the other hand, the memory devices require the step of forming capacitors, which require high-temperature and long-time heat processing after the gate electrodes have been formed, so that tungsten silicide, which has higher sheet resistance than titanium silicide and cobalt silicide, but is superior to titanium silicide and cobalt silicide in heat resistance, is applicable to the gate electrode of the memory device compatibly with steps of forming the memory elements.
It is one reason for applying tungsten silicide to the memory devices that the peripheral circuits of the currently fabricated memory devices are CMOS circuits of the so-called single gates which include the gate electrodes of the N-channel transistors and the gate electrodes of the P-channel transistors formed of N+ polycrystalline silicon. That is, the memory devices do not require high performance of the peripheral circuits, as do the logic devices, and accordingly it has not been much necessary to use the CMOS circuits of the so-called dual gates which include the gate electrodes of the N-channel transistors formed of N+ polycrystalline silicon, and the gate electrodes of the P-channel transistors formed of P+ polycrystalline silicon. Furthermore, diffusivity of dopants in tungsten silicide are several orders of magnitude higher than that in polycrystalline silicon, which has made it difficult to apply tungsten silicide to the CMOS circuits having the dual gates.
Recently, dual-gate CMOS technology is required even in peripheral circuits of memory devices in order to achieve high performance. However, high-performance circuits cannot be achieved in memory devices by using current dual-gate technology for LOGIC devices because of the poor thermal stability and severe inter-diffusion of gate dopants between P+ gate and N+ gate.
Presently, the so-called polymetal (polycrystalline silicon-metal) gate structures having a refractory metal and polycrystalline silicon laid on each other are considered. The polymetal structure has on polycrystalline silicon a layer of a refractory metal having higher heat resistance and lower sheet resistance than silicide, and can simultaneously satisfy low sheet resistance required by the logic devices, and heat resistance required by the memory devices.
A MOS transistor having the typical polymetal gate structure will be explained with reference to FIG. 12.
A gate electrode 104 is formed on a silicon substrate 100 intervening a gate insulation film 102 therebetween. The gate electrode 104 is formed of a layered structure of a polycrystalline silicon film 106 formed on the gate insulation film 102, a WN (tungsten nitride) film 108 formed on the polycrystalline silicon film 106 and a W (tungsten) film formed on the WN film 108. The WN film 108 is a barrier metal for preventing the polycrystalline silicon film 106 and the W film 110 from reacting with each other to thereby form tungsten silicide, which has high resistance. A cap film 112 of silicon nitride film is formed on the gate electrode 104. A silicon oxide film 114 is formed on the side walls of the polycrystalline silicon film 106. A sidewall insulation film 116 is formed on the side walls of the gate electrode 104. A source/drain diffused layer 122 formed of a low-concentration diffused region 118 and a high-concentration diffused region 120 is formed in the silicon substrate on both sides of the gate electrode 104.
The polymetal gate structure shown in FIG. 12 is much superior in heat resistance and in suppressing inter-diffusion of a dopant in the polycrystalline silicon film 106 in a case that the dual gate structure is adopted, whereby sheet resistance does not increase even after high-temperature and long-time heat processing and a threshold voltage of the transistors of the CMOS circuit does not change.
In the conventional method for fabricating the semiconductor device, an amorphous silicon film to be the polycrystalline silicon film 106 is deposited, boron is doped in the amorphous silicon film, the WN film 108 and the W film 10 are deposited, these laid films are patterned to form the gate electrode 104.
However, the semiconductor device having the polymetal structure fabricating by the above-described fabrication method often has depletion in the gate electrode 104 of the PMOSFET.
The inventors of the present application have made earnest studies of the depletion in the gate electrode 104 of the PMOSFET and has found for the first time that the depletion in the gate electrode 104 are caused by the fact that boron, a gate dopant of the PMOSFET is absorbed into the reaction layer between the WN film 108 as the barrier metal and the polycrystalline silicon film 106 to form B—N bonds, which lowers a boron concentration in the polycrystalline silicon film 106. The depletion in the gate electrode affect characteristics of the MOS transistor, and it is desirable to suppress the depletion as far as possible.